`timescale 1ns / 1ps

module delay_tb ();

    reg clk_50m, rst_n, busy_rx;
    reg [2:0] count_ms;
    wire delay_rx;

    initial begin
        $dumpfile("output/delay_tb.vcd");
        $dumpvars(0, delay_tb);
    end

    initial begin
        clk_50m = 0;
        rst_n = 0;
        #100 rst_n = 1;
        #100 
        busy_rx = 1;
        count_ms = 1;
        #100 busy_rx = 0;
        #2_000_000 
        busy_rx = 1;
        count_ms = 2;
        #100 busy_rx = 0;
        #10_000_000 $stop;
    end

    always #10 clk_50m <= ~clk_50m;

    delay delay_inst (
        .clk_50m            (clk_50m),
        .rst_n              (rst_n),
        .plus               (busy_rx),
        .count_ms           (count_ms),
        .delay              (delay_rx)
    );

endmodule  //delay_tb